The present invention relates to a capacitor structure and its method of fabrication for use in integrated circuits.
Dynamic random access memory (DRAM) relates to electronic devices consisting of cells which can retain information only for a limited time before they must be read and refreshed at periodic intervals. A typical DRAM cell consists of at least one transistor and a storage capacitor. In general, the integrated circuit used for DRAMs consists of metal oxide semiconductor (MOS) and particularly complementary MOS structures (CMOS) as the transistor component. Recently, the capacity of such DRAM structures has evolved from one megabit to on the order of one gigabit. This increase in memory has required the evolution of gate feature sizes on the order of 1.25 microns down to on the order of 0.25 microns or smaller. As the DRAM capacity requirements are increased, the requirements placed on the capacitors are increased as well. Not only is there a requirement for increased capacitance, there is also a requirement for decreased capacitor area. Accordingly, development efforts have been focused on materials and structures to meet this need.
To minimize interconnection resistance and to maximize the use of valuable chip area, advanced VLSI and ULSI logic integrated semiconductor circuits use multi-level wiring line structures for interconnecting regions within the devices and for interconnecting one or more devices within the integrated circuit. Multi-level metallization provides greater flexibility in circuit design, a reduction in die size and, thereby, a reduction in chip cost. In fabricating such structures, the conventional approach is to form lower level wiring lines (or interconnect structures) and then form one or more upper level wiring lines interconnected with the first level wiring lines. A first level interconnect structure may be, in contact with the doped region within the substrate of an integrated circuit device (for example the source or drain of a typical MOSFET). One or more interconnections are typically formed between the first level interconnect and other portions of the integrated circuit device or to structures external to the integrated circuit device. This is accomplished through the second and subsequent levels of wiring lines. An example of the multi-layer interconnect structure used in conventional VLSI and ULSI structures can be seen in FIG. 7. Conductive vias, shown generally at 701 are used to make the connection from one level to another. As is shown in FIG. 7, metal layer Mxe2x88x921 at the first level is connected to the source (S) 702 formed in the substrate layer of the integrated circuit. This metal layer Mxe2x88x921 is used to make electrical connections at level one as well as at higher levels using the via structure as shown.
An embedded DRAM structure adds integrated capacitors to the logic transistors to add high density memory cells to the circuit. These integrated capacitors can be connected to the source metallization of the MOS device to form the memory cell. Conventional DRAM capacitors often have a layer of polysilicon as the bottom electrode; a layer of silicon dioxide or silicon nitride as the insulator; and a top metal layer forming the top electrode. Such a structure is generally not compatible with embedded DRAM technology because of the added complexity of the poly-Si capacitors and the high temperatures required to grow the silicon oxide/nitride layer. For example, the aluminum metal layers used as interconnects in the multi-layer structure can be adversely affected by the relatively high temperatures used in the deposition of polysilicon. Furthermore, the use of polysilicon as an electrode can have deleterious affects on the electrical characteristics of the device. To this end, it is known to use tantalum pentoxide as the dielectric of the capacitor because of its a higher dielectric constant compared to silicon dioxide or silicon nitride. During the chemical vapor deposition used to form the tantalum pentoxide, a necessary layer of silicon dioxide is formed between the polysilicon layer and the tantalum pentoxide layer to prevent reduction of the tantalum pentoxide, and consequential leakage current. As can be appreciated, this layer of silicon dioxide is not desired in a capacitor, as it tends to adversely impact the capacitance of the capacitor. Accordingly, there is a need for a capacitor structure in DRAM""s, which avoids the use of polysilicon electrodes.
Trench capacitor structures are used in multi-layer integrated circuit (IC) structures to increase capacitance density compared to planar capacitors. While trench capacitors have enabled more efficient use of valuable chip real estate, applicants have recognized that known trench capacitor structures may not be adaptable to multi-layer fabrication techniques. In particular, planarization plays an important role in the fabrication of multi-layer integrated circuits. To this end, during the process of circuit fabrication, various growth and deposition techniques used to form insulating and conducting layers can result in an increasingly non-planar structure, which presents two major problems. The first problem is one of maintaining step coverage without breaks in the continuity of fine line structures. The second problem is a reduction in the optical resolution and therefore reduction in the ability to image fine-line patterns over the wafer structure. Accordingly, polishing techniques are used to maintain planarity at each level in a multi-level structure. One technique which has become widely embraced for planarization is chemical mechanical polishing (CMP). Such a polishing step would be utilized, for example after the fabrication of the capacitor in order to maintain a planar topology. After the fabrication of the capacitor, a CMP or other planarization step would be employed and subsequent deposition of metal and dielectric layers for the next level of the multi-level structure would be carried out. However, in known trench capacitor structures, CMP and other planarization techniques can have deleterious effects on the capacitor, for example shorting of the plates (electrodes).
Accordingly, the capacitor structures discussed above are not readily amenable to the processing techniques used in ULSI fabrication of multi-layer structures. What is needed is a capacitor structure which improves the capacitance density while being readily adaptable to standard/low temperature processing techniques and one which is compatible with chemical mechanical polishing used in multi-layer structures to maintain a desired level of planarity.
A capacitor structure is formed in an opening in a dielectric layer of an integrated circuit. The lower electrode (or plate) extends up at least a portion of the side surface(s) of the opening, but not onto the top surface of the dielectric. A layer of dielectric material is disposed on the lower electrode and upon the top surface of the integrated circuit dielectric. Finally, an upper electrode (or plate) is disposed on the layer of dielectric material. Because the lower electrode is removed from the top surface of the dielectric there is no overlap of the upper and lower electrodes along the top surface of the dielectric, thus avoiding shorting problems which could result during planarization.